1. Field of the Invention
This invention relates to arithmetic logic units, and more particularly to a method and circuit for performing overshifted rotate through carry instructions.
2. Description of the Relevant Art
Microprocessors determine the speed and power of personal computers, and a growing number of more powerful machines, by handling most of the data processing in the machine. Microprocessors typically include at least three functional groups: the input/output (I/O) unit, the control unit, and the arithmetic logic (ALU) unit. The I/O unit interfaces between external circuitry and the ALU and the control unit. I/O units frequently include signal buffers for increasing the current capacity of the signal before the signal is sent to external components. The control unit controls the operation of the microprocessor by fetching instructions from the I/O unit and translating the instructions into a form that can be understood by the ALU. In addition, the control unit keeps track of which step of the control unit is being executed. The ALU handles the mathematical computations and logical operations that are performed by the microprocessor. The ALU executes the decoded instructions received from the control unit to modify data contained in registers within the processor.
Essential components of most ALUs include circuitry for performing overshifted rotate through carry instructions. Rotate through carry instructions are divided into two types: rotate through carry left (RCL) and rotate through carry right (RCR). These instructions typically use a single bit carry flag as part of the rotation process in rotating an operand. In prior art ALUs, rotate through carry instructions required C cycles to complete, wherein C is the rotation count of the instruction. The RCL, in the first instruction cycle, shifts the carry flag into the least significant bit of the operand and shifts the most significant bit of the operand into the carry flag. The cycle is then repeated C times. Similarly, the RCR, in the first instruction cycle, shifts the carry flag into the most significant bit of the operand and shifts the least significant bit into the carry flag. The process is repeated C times.
Typical RCL and RCR instructions are formatted as follows:
(1) RCL A.sub.n-1:0,C.sub.z-1:0 PA1 (2) RCR A.sub.n-1:0,C.sub.z-1:0,
where A.sub.n-1 is the operand to be rotated and C is the rotation count. It is noted that the carry flag is not identified within the above instructions. However, it is presumed that the carry flag is involved in the execution of the rotate through carry instruction. The carry flag is typically stored within a dedicated register.
In normal rotate through carry instructions, the decimal equivalent of C is less than or equal to n, the number of bits or size of operand A. However, the decimal equivalent of C can be greater than n. When this occurs, the rotate through carry instruction is deemed "overshifted."
The prior art provides two methods for performing an overshifted rotate through carry instruction. The first method was briefly discussed above. In this first method, the prior art needs C cycles to complete an overshifted rotate through carry instruction, wherein each cycle involves shifting, the carry flag into either the least significant or most significant bit of the operand and shifting either the most significant or least significant bit of the operand into the carry flag, depending upon whether the rotation is in the left or right direction. This method is disadvantageous in that a significant amount processor time will be required to execute an overshifted rotate through carry having a large C.
In the second prior art method, the number of cycles needed to complete the overshifted instruction can be reduced when compared to the first method, given identical instruction parameters. Accordingly, this second prior art procedure is faster when compared to the first prior art method. The second method is performed by modifying the original overshifted rotate through carry instruction. In particular, modification involves first comparing rotation count C against n, the size of the operand to be rotated. If the rotation count is greater, the rotation count is divided down under the theory that rotating the combination of the operand and carry flag by (n+1) bit positions, results in the original operand and carry flag. Thus, in this second method, the rotation count is, in effect, divided by (n+1), with a new rotation count C.sub.new set to the remainder of the division. This second procedure, however, requires additional time and relatively complex hardware to divide the rotation count C by (n+1) and set the new rotation count to the remainder of the division.